| Publication Type |
dissertation |
| School or College |
College of Engineering |
| Department |
Electrical & Computer Engineering |
| Author |
Vij, Vikas S. |
| Title |
Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows |
| Date |
2013-12 |
| Description |
Asynchronous design has a very promising potential even though it has largely received a cold reception from industry. Part of this reluctance has been due to the necessity of custom design languages and computer aided design (CAD) flows to design, optimize, and validate asynchronous modules and systems. Next generation asynchronous flows should support modern programming languages (e.g., Verilog) and application specific integrated circuits (ASIC) CAD tools. They also have to support multifrequency designs with mixed synchronous (clocked) and asynchronous (unclocked) designs. This work presents a novel relative timing (RT) based methodology for generating multifrequency designs using synchronous CAD tools and flows. Synchronous CAD tools must be constrained for them to work with asynchronous circuits. Identification of these constraints and characterization flow to automatically derive the constraints is presented. The effect of the constraints on the designs and the way they are handled by the synchronous CAD tools are analyzed and reported in this work. The automation of the generation of asynchronous design templates and also the constraint generation is an important problem. Algorithms for automation of reset addition to asynchronous circuits and power and/or performance optimizations applied to the circuits using logical effort are explored thus filling an important hole in the automation flow. Constraints representing cyclic asynchronous circuits as directed acyclic graphs (DAGs) to the CAD tools is necessary for applying synchronous CAD optimizations like sizing, path delay optimizations and also using static timing analysis (STA) on these circuits. A thorough investigation for the requirements of cycle cutting while preserving timing paths is presented with an algorithm to automate the process of generating them. A large set of designs for 4 phase handshake protocol circuit implementations with early and late data validity are characterized for area, power and performance. Benchmark circuits with automated scripts to generate various configurations for better understanding of the designs are proposed and analyzed. Extension to the methodology like addition of scan insertion using automatic test pattern generation (ATPG) tools to add testability of datapath in bundled data asynchronous circuit implementations and timing closure approaches are also described. Energy, area, and performance of purely asynchronous circuits and circuits with mixed synchronous and asynchronous blocks are explored. Results indicate the benefits that can be derived by generating circuits with asynchronous components using this methodology. |
| Type |
Text |
| Publisher |
University of Utah |
| Subject |
Algorithms; Asynchronous circuits; Methodology; Relative timing; Synchronous CAD tools |
| Dissertation Name |
Doctor of Philosophy |
| Language |
eng |
| Rights Management |
Copyright © Vikas S. Vij 2013 |
| Format Medium |
application/pdf |
| Format Extent |
1,182,938 Bytes |
| Identifier |
etd3/id/3490 |
| ARK |
ark:/87278/s6gf42s0 |
| Setname |
ir_etd |
| ID |
197044 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6gf42s0 |
